As small cells are introduced into 4G networks, it becomes more important to create efficient MMIC power amplifiers
Small cells are being introduced into 4G networks to increase their capacity, especially in dense urban areas where macrocells are flooded with traffic.
Consequently, the power amplifiers (PA) of these small, highly distributed cells must be able to meet design criteria other than macrocells. They need to be able to handle less power (perhaps 60W peak for a 5W cell) because they transmit on shorter distances than macro cells and must be designed to ensure high efficiency, lower operating costs, and, light and cheap boxes.
One way to meet these design criteria is to use multistage LDMOS MMICs manufactured using high-volume silicon fabrication processes. These units offer high gain, integrated input and match between floors. They therefore meet the need for small and inexpensive PA, but their effectiveness is relatively low due to their use of integrated passive elements.
A solution developed by Ampleon is a semi-integrated 3-way 1: 2: 1 PA architecture that is both small and efficient. It has been successfully used to build a 60W MMIC at 2.14 GHz with a gain of 27.4 dB and an average energy efficiency (EEM) of 48.5% with an output power of 8 dB. The circuit has a size of 35 × 35 mm2 and, to our knowledge, currently offers the best performance at this frequency and performance level for a multi-stage MMIC.
Doherty architecture analyzed
This is a basic diagram of a PA built using a three-way Doherty architecture.
An important feature of a PA is its efficiency when operated at a power below its maximum power, which is referred to as a “back-off”.
The compact design equations can be used to locate the efficiency peaks 1 and 2 of a DPA as below, where 1 and 2 represent the capabilities of the standard 1 and 2-edge devices. Efficiency peaks can be expressed as follows:
The load modulation of the main device m can then be expressed as follows:
This gives high efficiency points at -2.50 dB (1 = 0.75) and -9.54 dB (2 = 0.33), with m = 2.25 for the power ratio (1: 1). 2: 1).
It is possible to simulate the voltage and current profiles of the PA, assuming that its transistors behave as ideal current sources with zero state voltage and constant direct conductivity, maximum current limit and power supply. 1V. We assume that the transistors operate in class B mode and that all harmonic impedances at the power source are shorted.
The above equations and simulations shown in Figure 2 indicate that from the viewpoint of efficiency, the 1: 2: 1 three-way DPA is better than the 1: 2 asymmetric DPA currently used in base stations. , DPA 1: 2: 1 maintains its efficiency above 67% to saturation point, while the efficiency of the 1: 2 DPA can decrease to 59% before returning to saturation. This means that the 1: 2: 1 DPA is expected to achieve an average yield that is 6 percentage points higher than that of the 1: 2 DPA in the desired 8 to 9 dB fade range.
That’s the theory. What happens in reality? We can calculate the practical power modulation mode of the main unit, knowing that m is 2.25 for DPA 1: 2: 1 and 3 for DPA is 1: 2. With real devices that do not have zero-resistance and zero-output RF losses, the actual power modulation of the three-channel DPA is lower than the theory suggests. This gives us a real efficiency point of 1: 2 DPA decrease at -7.8 dB (real = 0.41). Using a real mod of 1.58 instead of a theoretical 2.25, the second real backup efficiency point 2 of the 1: 2: 1 DPA is -8 dB.
These calculations show that the efficiency of the 1: 2: 1 DPA is maintained or even slightly increased thanks to its additional peak efficiency in delayed mode. This gives a better average efficiency in the retreat zone of 8 to 9 dB.
A good AP also requires good linearity. One of the challenges of the 1: 2: 1 DPA architecture has been to implement effective practical implementations using passive input delimiters. The problem is that for better efficiency, the current to the main unit must remain saturated and constant from the first memory point 1 to -6 dB to the full power state. This can lead to a disturbance of the main amplifier load when peak1 reaches the voltage saturation at 1. This creates linearity problems that require modulation schemes as used in GSM multi-carriers that require performance. Intermodulation above -60dBc.
One solution is to use independent disk profiling for each amplifier, but this complicates the practical implementations so that the approach becomes priceless for most base stations.
Our integrated Doherty implementation (iDPA) replaces the standard Doherty impedance inverter with a p-network of parasitic drain-source capacitors (CDS_M and CDS_P) of the main and peak transistors and an inductor connected together are. ,
We used this approach to construct a 1: 2: 1 three-way DPA by combining a dual amplifier and a single amplifier into a two-channel package (see Figure 3) to reduce the overall size.
The three-way DPA was fabricated on a standard 20 mil thick circuit board with a dielectric constant of 3.5.
Figure 3 compares gain and PAE for DPA 1: 2: 1 and 1: 2 architectures: The 1: 2: 1 amplifier achieves a maximum gain of 27.4 dB at 2.14 GHz and an average PAE of 47, 5% at 8 dB recoil, measured with a 20 MHz LTE signal with a peak to mean ratio of 7.2 dB.
The three-way DPA can be linearized at this power level to achieve an adjacent channel power ratio of -58 dBc using digital predistortion. Comparing the performance of the 1: 2: 1 DPA implementation with the iDPA 45W 1: 2 MMIC stand-alone performance, which is part of the three-way architecture, the three-way configuration provides an improvement of 3 , 5%. PAE, at the expense of 2 dB gain.
In summary, this 1: 2: 1 semi-integrated 1: 2: 1 Doherty architecture integrates a dual-channel device with another amplifier in a small package for superior performance. This demonstrates that DPA MMICs can be used to build efficient and economical small cell base stations.